The present invention is related to a circuit and method for reading data transfers, and is more particularly related to reading data transfers that are sent with a source synchronous clock signal.
When sampling double data rate, (DDR) data transfers that are sent with a source synchronous clock, such as in SDRAM-DDR memory devices, the requirement for correct interface operation is that the incoming data is safely sampled during a known internal clock cycle. The total number of cycles required for transmission is not important if the data can be transferred into a predetermined internal clock cycle. Because the arrival of the incoming clock and data signals can vary greatly with respect to the desired internal sample cycle, this is often a difficult task.
There is thus a need to be able to correctly sample incoming DDR data over a wide range of arrival times with minimal latency added to the receiving of that data and with substantial immunity from spurious noise signals on the source synchronous clock and data, such as occurs during switching from accessing one memory device to accessing another memory device sharing a common clock and data line. The circuit of the present invention can be used to receive data and clock signals from two or more different sources that share the same electrical connections with different transmission times, (as is the case when multiple SDRAM-DDR memory devices share a common data interface to a controlling chip) as long as the range of arrivals is within the tolerances of the receiving circuit.
The circuits in this invention sample incoming, source synchronous, DDR data by: stretching the incoming even and odd transfers of data signals using latches clocked by an appropriately delayed data strobe signal; capturing this stretched data into intermediary clock domain latches that have their clocks delayed to safely capture all possible arrivals of stretched, incoming data; transferring this intermediary latch data into a latch on the internal clock domain during the programmed, internal target arrival cycle. The advantages of this approach over simply latching the incoming data with the delayed data strobe and then transferring into the local clock domain are as follows. If a transparent latch is used to capture the incoming data with the delayed data strobe the otherwise added latency of one half of a bit time can be avoided. Also, by using an intermediary latch to sample the stretched data captured by the data strobe, a greater range of data arrivals with respect to the internal target arrival cycle can be tolerated.